1. Field of the Invention
The present invention relates to a voltage level shifter and a display device incorporating such a voltage level shifter. Such a shifter may, for example, be used in large area silicon-on-insulator (SOI) circuits for interfacing with signals of smaller amplitudes. An example of such an application is monolithic driver circuitry for flat-panel matrix displays, such as liquid crystal displays, fabricated with low temperature poly-silicon thin-film transistors (TFTs) whore interfacing between signal levels of 3.3 to 5 volts and signals of 10 to 20 volts is often required.
2. Description of the Related Art
FIG. 1 of the accompanying drawings illustrates a known type of CMOS inverter, for example as disclosed in A. Bellaouar, M. Elmasry, xe2x80x9cLow Power Digital VLSI Designxe2x80x9d, Kluwer Academic Publishers, 1995, which may be used to provide a limited range of level shifting. The inverter comprises a P-type transistor T1 and an N-type transistor T2 connected in series between a power supply line vdd and ground gnd. The drains of the transistors T1 and T2 are connected to an output !OUT for providing inverted output signals and the gates of the transistors are connected together to input IN.
A disadvantage of such an arrangement for implementation in TFT circuits is that the input voltage level must be greater than the switching point. However, this condition is difficult to achieve with low performance transistors having highly variable transistor characteristics. For example, typical signal levels produced in conventional large scale integrated circuits as used in active matrix liquid crystal display (AMLCD) interface circuitry range from 2.7 to 5.5 volts. The switching point of the inverter should range from 1.35 to 2.5 volts depending on the desired noise margin.
FIG. 2 of the accompanying drawings illustrates a typical switching characteristic of a CMOS inverter of the type shown in FIG. 1 as a function of the transistor characteristics and the supply voltage Vdd. The switching point Vth of the inverter is defined as the input voltage at the intersection of Vin=Vout and is given by:       V          t      ⁢              xe2x80x83            ⁢      h        =                    V                  T          ⁢                      xe2x80x83                    ⁢          h                    +                                                  β              ⁢                              xe2x80x83                            ⁢              p                                      β              ⁢                              xe2x80x83                            ⁢              n                                      ⁢                  (                                                    V                ⁢                                  xe2x80x83                                ⁢                d                ⁢                                  xe2x80x83                                ⁢                d                            -                        |                          V                              T                ⁢                                  xe2x80x83                                ⁢                p                                      |                    )                            1      +                                    β            ⁢                          xe2x80x83                        ⁢            p                                β            ⁢                          xe2x80x83                        ⁢            n                              
where xcex2p and xcex2n are the transconductances and Vtp and Vtn are the threshold voltages of the P-type transistor T1 and the N-type transistor T2, respectively.
The range of transistor parameters for which the inverter will switch with a given input voltage defines a xe2x80x9cprocess marginxe2x80x9d. As illustrated by the above expression, in order to achieve low input voltage operation, it is necessary to ensure a low threshold voltage and a high mobility of the N-type transistor T2. Also, the switching point of the inverter increases with the supply voltage Vdd. In order to improve the performance of level shifters based on such inverters, it is known to connect several inverters in series and to apply different supply voltages to the inverters. However, level shifters of this type are not suitable for applications in which the transistor performance is not well defined and where a large signal level shift is required.
Another known type of level shifter is shown in FIG. 3 of the accompanying drawings and in based on differential techniques as used, for example, in sense amplifiers of memory circuits. Such a CMOS sense amplifier is also disclosed in Bellaouar at al (see above) and comprises P-type transistors T3 and T4 and N-type translators T5, T6 and T7. The transistors T5 and T6 form a differential pair with the transistor T7 acting as a tail current source with its gate connected to a terminal Vb for receiving a bias voltage. The transistors T3 and T4 are connected between the drains of the transistors T5 and T6, respectively, and the supply line vdd. The gate of the transistor T3 is connected to the drains of the transistors T4 and T6 and to an output terminal OUT whereas the gate of the transistor T4 is connected to the drains of the transistors T3 and T5 and to an output terminal !OUT for supplying inverted output signals. The gates of the transistors T5 and T6 are connected to complementary inputs IN and !IN for receiving complementary input signals.
Assuming that the transistors are perfectly matched and identical differential input voltages ate supplied to the inputs IN and !IN, the tail current set by the bias voltage flows in equal portions through the transistors T5 and T6 and hence through the transistors T3 and T4. This condition is meta-stable and changes in response to any perturbations of the differential input voltage. For example, if the voltage at the input IN is slightly larger than that at the input !IN, the transistor T5 turns on more than the transistor T6. This has the effect of lowering the voltage at the output !OUT. The transistor T4 is turned on more which increases the voltage at the output OUT. The transistor T3 is turned off further, which lowers the voltage at the output !OUT and increases the voltage at the output OUT. Thus, a slight imbalance in the input voltages is sensed and amplified at the output terminals !OUT and OUT.
A limitation of this type of circuit as a level shifter is that it requires that the logic high input levels supplied to the inputs be significantly higher than the threshold voltages of the N-type transistors. However, when embodied as a monolithic integrated circuit driver for an AMLCD, the threshold voltages of the N-type transistors can be as high as 4.5 volts.
For more efficient operation at lower input voltages, the conduction types of the transistors may be reversed to provide an arrangement as illustrated in FIG. 4 of the accompanying drawings, thus, the transistors T3 and T4 are N-type transistors whereas the transistors T5, T6 and T7 are P-type transistors. However, a disadvantage of this arrangement in that, when a high supply voltage Vdd and low input voltages are used, the transistors T5 and T6 operate in the linear regime. Differential amplifiers are much more efficient when the input transistors are operated in the saturated regime. In this condition, the difference in currents is greatest for a given differential input voltage so that the gain is higher for a given tail current.
FIG. 5 of the accompanying drawings illustrates another known type of level shifter in the form of a source follower, P-type transistors T8 and T9 are connected in series between the supply line vdd and ground gnd. The drain of the transistor T8 is connected to the source of the transistor T9 and to an output OUT. The gate of the transistor T8 is connected to receive the bias voltage Vb and the gate of the transistor T9 is connected to an input terminal IN, when the transistors T8 and T9 are in saturation, the output voltage is shifted positively by (VDDxe2x88x92Vb), assuming that the transistors T8 and T9 are matched. Two such level shifters may be used to drive a differential amplifier of the type shown in FIG. 3 or 4 in order to solve the problem of high N-type device threshold voltage or to maintain P-type devices in saturation. However, a disadvantage of such an arrangement arises from the many DC current paths.
According to a first aspect of the invention, there is provided a voltage level shifter comprising first and second voltage followers arranged to receive bias voltages from the second and first voltage followers, respectively.
According to a second aspect of the invention, there is provided a voltage level shifter comprising first to fourth transistors of a first conduction type, the first and second transistors being connected in series between first and second power supply inputs with the control electrode of the second transistor being connected to a first input for receiving a direct input signal, the third and fourth transistors being connected in series between the first and second power supply inputs with the control electrode of the fourth transistor being connected to a second input for receiving a complementary input signal, the control electrode of the first transistor being connected to the output electrode of the third transistor and the common electrode of the fourth transistor, and the control electrode of the third transistor being connected to the output electrode of the first transistor and the common electrode of the second transistor.
The source of at least one of the second and fourth transistors may be connected to an output circuit.
The output circuit may comprise an inverter. The inverter may comprise a fifth transistor of the first conduction type and a sixth transistor of a second conduction type different from the first type connected in series between the first and second power supply inputs, the control electrodes of the fifth and sixth transistors being connected to the source of one of the second and fourth transistors. Seventh and eighth transistors of the second conduction type may be connected in parallel with the second and fourth translators, respectively, with the control electrodes of the seventh and eighth transistors being connected to the second and first inputs, respectively.
The output circuit may comprise a differential amplifier whose differential inputs are connected to the sources of the second and fourth transistors. The differential amplifier may comprise ninth and tenth transistors of the first conduction type whose control electrodes are connected to the sources of the second and fourth transistors, respectively, and whose drains are connected to a current mirror.
The output of the differential amplifier may be connected to an inverter. The input of the inverter may be connected to a first pull-up or pull-down transistor whose control electrode is connected to a gating input.
One of the differential amplifier inputs may be connected to a second pull-up or pull-down transistor whose control electrode is connected to a gating input.
One of the first and second power supply inputs may be connected to the first to fourth transistors and the differential amplifier via an eleventh transistor whose control electrode is connected to a gating input.
The first and second inputs may be connected to control electrodes of the second and fourth transistors via twelfth and thirteenth transistors, respectively, whose control electrodes are connected to a gating input.
Each of the transistors may be field effect transistor whose common, control and output electrodes are source, gate and drain electrodes, respectively. Each of the transistors may be a thin film transistor.
The first conduction type may be P-type.
The shifter may comprise at least part of a CMOS integrated circuit.
The shifter may be connected to a display device.
The display device may be a flat-panel matrix display, especially an LCD device.
The LCD device may be an AMLCD.
According to a third aspect of the invention, there is provided a level shifting circuit comprising an input stage having first to fourth transistors of a first conduction type, the first and second transistors form a first source follower and are connected in series between first and second power supply inputs with the control electrode of the second transistor being connected to a first input for receiving a direct input signal, the third and fourth transistors form a second source follower and are connected in series between the first and second power supply inputs with the control electrode of the fourth transistor being connected to a second input for receiving a complementary input signal, the control electrode of the first transistor being connected to the output electrode of the third transistor and the common electrode of the fourth transistor, and the control electrode of the third transistor being connected to the output electrode of the first transistor and the common electrode of the second transistor; and an output stage, wherein the source of at least one of the second and fourth transistors is connected to the output stage.
The output stage may be an amplifier.
The amplifier may be a CMOS inverter.
The first to fourth transistors may be P-type transistors.
According to the fourth aspect of the invention, there is provided a display device having:
a matrix having elements corresponding to pixels of the display;
at least one driver connected to the matrix to drive the matrix;
an input device for receiving external input signals via input terminals, the input device being connected to the at least one driver for outputting level shifted signals;
wherein the input device comprises a voltage level shifter of the present invention, and the first to fourth transistors are P-type transistors.
The input terminals may be directly connected to the control electrodes of the second and fourth transistor.
The matrix may be the matrix of an AMLCD.
The at least one driver may be a gate driver and/or a source driver.
The driver may be implemented in poly-Silicon having thin film transistors as switching elements.
It is thus possible to provide a level shifter which is capable of providing large shifts in signal levels and which has a wide process margin. Only one conduction type of transistor is required at the input so that there is no need to consider matching between N-type and P-type transistors. Such an arrangement also provides controlled current consumption with the cross-coupling ensuring that the majority of the quiescent flows in only one of the voltage followers.